1. Field of the Invention
The present invention relates to a semiconductor wafer with an epitaxial coating on a front surface which has improved flatness and a reduced number of light scattering centers on the epitaxial layer, and to a cost-effective process for producing it. Semiconductor wafers of this type are suitable for use in the semiconductor industry, in particular for the fabrication of electronic components with line widths of less than or equal to 0.13 μm.
2. The Prior Art
A semiconductor wafer which is intended to be suitable in particular for the fabrication of electronic components with line widths of less than or equal to 0.13 μm must have a large number of special properties. A particularly important property is the local flatness of the semiconductor wafer. The modern stepper technology requires optimum local flatness in all partial regions of a surface of the semiconductor wafer. This can be expressed for example as SFQR (site front-surface referenced least squares/range=range of the positive and negative deviation from a front surface defined by minimizing the mean square error for a component area of defined size). The quantity SFQRmax specifies the maximum SFQR value for all the component areas on a semiconductor wafer. A generally accepted rule of thumb states that the SFQRmax value of a semiconductor wafer must be less than or equal to the possible line width on this wafer for semiconductor components that are to be produced on it. If this value is exceeded, the stepper experiences focusing problems and the component in question is thus lost.
A further important property of semiconductor wafers is the number of light scattering centers (localized light scatterers, LLS) on the surface on which semiconductor components are intended to be produced. When they are present in a certain number and size, LLS can lead to the failure of the components. The final flatness of a semiconductor wafer is generally produced by a polishing process. In order to improve the flatness values of a semiconductor wafer, apparatuses and processes for the simultaneous polishing of front and rear surfaces of the semiconductor wafer have been provided and developed further. An example of this double-side polishing is described in U.S. Pat. No. 3,691,694.
In accordance with an embodiment of double-side polishing which is described in EP 208,315 B1, semiconductor wafers in carriers which are made of metal or a plastics material and have suitably dimensioned cutouts are moved along a path. This path is predetermined by the machine and process parameters between two rotating polishing plates, which are covered with a polishing cloth, in the presence of a polishing slurry and are thus polished. The German Patent Application No. 19,905,737.0 describes a double-side polishing process which leads to semiconductor wafers with improved flatness principally in the edge region. In this case, carriers are used whose thickness is dimensioned in such a way that the final thickness of the wafers after they have been polished is only 2 to 20 μm greater than the thickness of the carriers.
Monocrystalline semiconductor wafers may have a layer of the same crystal orientation grown thereon in a monocrystalline manner. This is a so-called epitaxial or epitaxially grown layer, on which semiconductor components are applied. Thus,for example a silicon wafer with a silicon layer will have certain advantages over semiconductor wafers made of a homogeneous material. Mention may first be made of the so-called latch-up problem, which can occur for example in bipolar CMOS circuits on homogeneous material. This can lead to voltages in the bipolar transistors which may permit charge reversal and effect a short circuit of the components in question. The person skilled in the art is aware that this latch-up problem can be effectively prevented by the use of an epitaxially coated semiconductor wafer. This wafer is made of a heavily doped substrate wafer (low electrical resistance) and a weakly doped epitaxial layer (high resistance). This simultaneously brings about a desirable gettering effect of the substrate and, moreover, reduces the area occupied by the component. Furthermore, in comparison with polished semiconductor wafers, epitaxially coated surfaces have a lower defect density, expressed as LLS. This may be so-called COPs (crystal-originated particles), for example, which generally leads to a higher yield of intact semiconductor components. Furthermore, epitaxial layers have no appreciable oxygen content, which precludes the risk of oxygen precipitates that potentially destroy circuits in regions relevant to components.
According to the prior art, epitaxially coated semiconductor wafers are produced from suitable intermediates by the process sequence of stock-removing polishing—final polishing—cleaning—epitaxy. In this case, depending on the process control, the surface roughness is approximately 0.5 to 3 nm RMS (root mean square) after the stock-removing polishing, measured by the atomic force microscope method (AFM) in a region of 1 μm×1 μm, and approximately 0.05 to 0.2 nm RMS after the final polishing.
Three-stage or four-stage polishing processes in which the roughness is progressively decreased are likewise known. EP 684,634 A2 describes another procedure in which, in the stock-removing polishing step, two different polishing slurries of different granularity are supplied one after the other before the semiconductor wafers are subjected to a final polishing step. Multi-stage polishing processes have the disadvantage that the production costs of the semiconductor wafers rise with each additional step.
EP 711,854 A1 describes a process for producing an epitaxially coated wafer by subjecting a sawn-lapped-etched silicon wafer to stock-removing polishing. In this case a surface roughness of 0.3 to 1.2 nm RMS (AFM, 1 μm×1 μm) is established. In order to reduce the costs, an epitaxial silicon layer is deposited without a smoothing final polishing step being carried out. The epitaxial layer thus produced is comparable in its electrical properties to an epitaxial layer produced conventionally with prior application of a final polishing step. However, there is an increase in light scattering centers on the epitaxially coated surface. This increase is caused by the relatively high starting roughness, and therefore potentially leads to increased failure of components produced on these wafers.